Please check the clock ratio settings of CPU clock and bus clock.
When the ratio of CPU clock cycle to bus clock cycle is 1:1, it cannot be accessed to the SDRAM.
When the burst access is generated to the SDRAM under that setting, the interlock works inside the SH and the SH operation could possibly stop.
When the cache is disabled, the burst access to the SDRAM would not be generated so that it seems to be normally operated but the proper operation is not guaranteed.
Therefore, it should not set the ratio of CPU clock to bus clock to 1:1 when the SDRAM is used.