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When are TABT bit and RABT bit of EtherC/E-DMAC status register set?

Latest Updated:03/25/2009

Question:

When are both TABT bit (transmit interruption detection) and RABT bit (receive interruption detection) of EtherC/E-DMAC status register (EESR) set?

Answer:

•TABT bit(transmit interruption detection)

When either of following bit in EtherC/E-DMAC status register (EESR) is set, the TABT bit is set at the same time.

 bit11:CND bit (Not career found)
 bit10:DLC bit (Career lost found)
 bit9 :CD bit (Collision found)
 bit8 :TRO bit (Transmit retry over)

・ RABT bit (Receive interruption detection)

When either of following bit in EtherC/E-DMAC status register (EESR) is set, the RABT bit is set at the same time.

 bit4 :RRF bit (Fraction bit frame receive)
 bit3 :RTLF bit (Long frame receive error)
 bit2 :RTSF bit (Short frame receive error)
 bit1 :PRE bit (PHY-LSI receive error)
 bit0 :CERF bit (Receive frame CRC error)

However, the RABT bit is not set when the RMAF bit of bit7 (multicast address frame receive) is set.

Suitable Products
SH7619
SH7618