Please check the following.
1) Is each power supply supplied correctly?
2) Is a correct potential applied?
3) Are clocks input to SH-4?
4) Is RESET negated(High)?
5) Is MRST negated(High)?
6) When using H-UDI: Is TRST driven low for a period overlapping RESET at power-on?
When not using H-UDI: Is TRST fixed to the ground or connected to the same signal line as RESET?
7) Are MODE<8:0> or MODE<10:0> fixed to each setting level ('High" or 'low')?
8) Does CKIO output expected frequency?
9) Is access to Area0 performed after releasing a power-on reset
(SH-4 accesses to h'a000 0000 when a power-on reset is released).
10) Is RDY asserted (low)? (RDY at high means wait.)
11) CA pin is reserved pin in the SH7750, but please pull up CA pin at +3.3V.
(CA pin must be pulled up externally when hardware standby is not used).