The delay cycles of the CS assert and the CSn negate can be extended to 0.5 and 1.5 cycles respectively by the SW[1:0] bit and the HW[1:0] bit of the CSn space wait control register (CSnWCR).
- Is it correct to say that 2 cycles are added to the Th and Tf respectively when 2.5 cycles are set to the bits.
- Is the fractional portion of 0.5 cycles equivalent to the standard value of "1/2tcyc" for the address delay time1 (tAD1) and CS delay time1 (tCSD1)?
- 2 cycles are added to the Th when 10:2.5 cycle is set to the SW[1:0] bit, and 2 cycles are added to the Tf when 10:2.5 cycle is set to the HW[1:0] bit.
- As you mentioned.
|SH7131, SH7132, SH7136, SH7137|
|SH7083, SH7084, SH7085, SH7086|