Does the MTU run in the bus release state?
If the timer counter started before the transition to the bus release state, the timer counting and the output from the PWM output pin continue even after the transition to the bus release state. However, the CPU stops processing in the bus release mode, so a flag clearance or register setting cannot be made, even if interrupt requests are generated. Please return the bus mastership to the CPU by asserting the IRQOUT# signal, when it must process an interrupt.
|SH7047, SH7049, SH7105, SH7107, SH7109|
|SH7040, SH7041, SH7042, SH7043, SH7044, SH7045|