What does an interrupt is not generated mean?

Please check the following.
- Is the PSW.I bit (interrupt enable bit) of the CPU set to 1 (interrupt enabled)?
- Is the interrupt request enable bit (IERm.IENj) set to 1 (interrupt request is enabled)?
- Is the interrupt priority level (IPRn.IPR[3:0] bit) > the PSW.IPL[3:0] bit?
- Have interrupts been enabled in the peripheral function register? (Example: For the MTU, is the bit corresponding to the interrupt source in the timer interrupt enable register (TIER) set to 1 (interrupt request is enabled)?)
- Check that the interrupt request destination has not been set to DMAC or DTC (see "Selecting Interrupt Request Destinations" in the "Interrupt Controller (ICUb)" chapter of the user's manual: hardware).