Failure to Capture Input During Cascade Connections

Please check the following items:

(1) Input capture setting enabled both for MTU1 and MTU2

The input capture for MTU1 is taken as the input capture for MTU2 internally and vice versa. Therefore, MTU1 and MTU2 should be set at the same value in the timer I/O control register (TIOR) setting. 

(2) Terminals not used for input capture set high

When the I2AE bit of the input capture control register (TICCR) is set to "1", the input capture terminal of MTU1 becomes both MTIOC1A and MTIOC2A. At this time, edge detection for the input capture condition is performed at the signal from a logical OR of MTIOC1A and MTIOC2A terminal input levels, and if one of the inputs is high, no edge detection happens even if the other one changes. 
Change the terminal not used for input capture to low or specify its terminal function to something besides MTU (such as general I/O port).
When the terminal function is set to something besides MTU (such as general I/O port), it is internally tied low.