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What does latch-up-proof architecture mean in UPD5200, 5201 and 5205?

Latest Updated:09/01/2007

Question:

In the UPD5200, 5201, and 5205's datasheets, what does "latch-up-proof architecture" mean? Does it mean that the architecture does not cause latch-up?

Answer:

Since it is CMOS architecture, it could, in principle, cause latch-up.
"Latch-up-proof" does not mean that latch-up is prevented, but latch-up does not occur easily (that is, latch-up tolerance is improved compared to existing architecture).
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