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What conditions does latch-up occur with the UPD5200, 5201, and 5205?

Latest Updated:09/01/2007

Question:

Under what conditions does latch-up occur with the UPD5200, 5201, and 5205?

Answer:

If the potential of the power supply, GND pin, or S or D pin is in one of the following conditions, the IC can be damaged.

  • If voltage is applied to the S or D pin when no power voltage is applied to the power supply pin V +. (Because the parasitic diode consisting of channel P and substrate N turns on and overcurrent flows, if S or D potential becomes higher than V +.)
  • If GND pin voltage becomes at least VF (diode forward breakdown voltage ≈ 0.7 V) higher than V+ pin voltage. (Because high current flows from the GND pin to Nsub.)

Especially in this case, if the potential of the S or D pin is low (such as being the same level as V-), it's liable to break at the same time of power application.
Note the power-on sequence. Even if the power supply source itself were to activate quickly, the potential on the power supply pin could be delayed by the effect of filters existing in the power supply line to the power supply pin of the IC.

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