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Can you please explain in detail about Interrupt specifications?

Latest Updated:12/07/2004

Question:

(Interrupts)   [Specification],[Interrupt priority level] and [Processing details] of multiple interrupts are as follows;
[Specification]
Interrupt 1 : Disable multiple interrupts
Interrupt 2 : Enable multiple interrupts
Interrupt 3 : Enable multiple interrupts other than those enabled by interrupt 2
[Interrupt priority level]
Interrupt1 > Interrupt 2 > Interrupt 3
[Processing details]
Interrupt 1 :
(snip)
RTI
Interrupt 2 :
CLI
(snip)
RTI
Interrupt 3 :
CLB 0, ICON1 (Set the interrupt enable bit of the interrupt 2 to "disable")
CLI
(snip)
SEI
SEB 0, ICON1 (Set the interrupt enable bit of the interrupt 2 to "enable")
RTI
1. What happens to the process when am interrupt 2 request is generated during processing of interrupt 3?
2. What happens to the process when simultaneous interrupt 2 and 3 requests are generated?
3. What points need to be considered in regards to multiple interrupt design?
[2004/12/07]

Answer:

  1. Interrupt 2 is processed after interrupt 3 processing completes. Even if the interrupt 2 request is generated while the interrupt 2 enable bit is disabled, the request bit is retained.
  2. According to the priority level, interrupt 2 is processed first. An interrupt is acknowledged immediately after the CLI instruction which enables multiple interrupts in interrupt 2, and interrupt 3 is processed.
  3. Check the following points for possible system problems.
    • When an interrupt request of lower priority level is generated twice or more within a higher-priority interrupt, the interrupt request will be recognised as once.
    • Since interrupts 2 and 3 recognise their own interrupts during execution, the same process may be executed multiple times.

(#104928)

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