In the User's Manual, there is a description saying, "No interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction."
Are interrupts disabled in this period (7 clocks)?
No. The description "between an interrupt request non-sample instruction and the next instruction" means a period in which the CPU does not perform interrupt acknowledgement (sampling).
That is, you should understand that a non-sample instruction and the next instruction are always executed in succession. [All V850]
(This 7-clock period refers to the period from the time an EI instruction is executed in the DI state to the time the CPU is enabled to acknowledge an interrupt. It has no relation to interrupt disabling.) [All V850/S series]